IBPS SO IT Officer Professional Knowledge Quiz – Computer Architecture – 5

Hello and welcome to exampundit. Here is a set of IBPS SO IT Officer Professional Knowledge Quiz on Computer Architecture for IBPS IT Officer Mains exam 2018.

IBPS SO IT Officer Professional Knowledge

  1. Register renaming is done in pipelined processors

(a) as an alternative to register allocation at compile time

(b) for efficient access to function parameters and local variables

(c) to handle certain kinds of hazards

(d) as part of address translation

(e) None of these

Answer

Option: C

Explanation:

Register remaining is done is pipelined processors to handle certain kinds of hazards.

 

  1. The amount of ROM needed to implement a 4 bit multiplier is

(a) 64 bit

(b) 128 bit

(c) 1 kbit

(d) 2 kbit

(e) None of these

Answer

Option: D

Explanation:

The normal size of ROM is n × 2n

Now, we are multiplying two n-bit numbers.

So, the resultant has 2n bit.

Hence, the size of the ROM is 2n × 22n

In the question, n = 4

Hence, >> 2 × 4 × 22×4

>> 8 × 28 >> 23 × 28

>> 2 × 210 >> 2 k bit

 

  1. Let the page fault service time be 10 Ms in a computer with average memory access time being 20 ns. If one page fault is generated for every 106 memory accesses, what is the effective access time for the memory?

(a) 21 ns

(b) 30 ns

(c) 23 ns

(d) 35 ns

(e) None of these

Answer

Option: B

Explanation:

 

 

  1. A computer handles several interrupt sources of which of the following are relevant for this question.

    Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high)
    Interrupt from Mouse (raises Interrupt if the mouse is moved or a button is pressed)
    Interrupt from Keyboard (raises Interrupt if a key is pressed or released)
    Interrupt from Hard Disk (raises Interrupt when a disk read is completed)

Which one of these will be handled at the HIGHEST priority?

(a) Interrupt from Hard Disk

(b) Interrupt from Mouse

(c) Interrupt from Keyboard

(d) Interrupt from CPU temperature sensor

(e) None of these

Answer

Option: D

Explanation:

Higher priority interrupt levels are assigned to requests which, if delayed or interrupted, could have serious consequences. Devices with high speed transfer such as magnetic disks are given high priority, and slow devices such as keyboard receive low priority. We know that mouse pointer movements are more frequent than keyboard ticks. So its obvious that its data transfer rate is higher than keyboard. Delaying a CPU temperature sensor could have serious consequences, overheat can damage CPU circuitry. From the above information we can conclude that priorities are-

CPU temperature sensor > Hard Disk > Mouse > Keyboard

 

  1. How many 32 k × 1 RAM chips are needed to provide a memory capacity of 256 kbyte?

(a) 8

(b) 32

(c) 64

(d) 128

(e) None of these

Answer

Option: C

Explanation:

As given, basic RAM is 32 k × 1 and we have to design a RAM of 256 k × 8.
Therefore, number of chips required
= 256 k × 8/(32 k × 1)
= 245 × 1024 × 8/32 × 1024 × 1)
(Multiplying and dividing by 1024)
= 64 = 8 × 8
Means, 64 = 8 parallel lines × 8 serial RAM chips.

 

  1. A CPU generally handles an interrupt by executing an interrupt service routine

(a) as soon as an interrupt as raised

(b) by checking the interrupt register at the end of fetch cycle

(c) by checking the interrupt register after finishing the execution of the current instruction

(d) by checking the interrupt register at fixed time intervals.

(e) None of these

Answer

Option: C

Explanation:

The interrupt register is checked after finishing the execution of the current instruction. At this time, a CPU generally handles an interrupt by the execution of an interrupt service routine.

 

  1. For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to

(a) non-uniform distribution of requests

(b) arm starting and stopping inertia

(c) higher capacity of tracks on the periphery of the platter

(d) use of unfair arm scheduling policies

(e) None of these

Answer

Option: C

Explanation:

The seek latency is not linearly proportional to seek distance due to the higher capacity of tracks on the periphery of the latter. The higher capacity of the tracks is responsible for the presence of this certain amount of time is required for this cells to reach the read-write head so that data transfer can take place.

 

  1. Consider a 4-way set associate cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively.

(a) 9, 6, 5

(b) 7, 7, 6

(c) 7, 5, 8

(d) 9, 5, 6

(e) None of these

Answer

Option: B

Explanation:

7 bits are required if there are 128 lines. The reason behind is that 128 is 27.

Now, each line is of 64 words or 26 words.

Hence, number of bits required is 6 bit as 64 or 26.

As per the given, a 20 bit address is generated for a word in main memory, so bits required for tag

= 20 – (7 + 6) = 20 – 13 = 7 bit.

 

 

  1. Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 byte of data are stored in a bit serial manner in a second. The capacity of the disk pack and the number of bits required to specify a particular section in the disk are respectively

(a) 256 Mbyte, 19 bit

(b) 256 Mbyte, 28 bit

(c) 512 Mbyte, 20 bit

(b) 64 Gbyte, 28 bit

(e) None of these

Answer

Option: A

Explanation:

The formula used is

Total disk size is given by = Number of surfaces ×

Number of tracks × Number of sectors × Capacity of each sector.

Therefore from the given data, we get

Total disk size = 16 × 128 × 256 × 512 byte

= 28 × 220 = 28 megabyte = 256 MB

Total number of sectors = 16 × 128 × 256 byte

= 219 byte

 

  1. A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

(a) 400

(b) 500

(c) 600

(d) 700

(e) None of these

Answer

Option: A

Explanation:

Each address is multiple of 3 as the starting address is 300 and is each instruction consists of 24 bit, i.e., 3 byte.

 

Regards

Team EP

 

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